1. Field of the invention
The present invention relates generally to a method of manufacturing a phase change RAM device. More particularly, the present invention relates to a method of manufacturing a phase change RAM device capable of effectively lowering the level of current required for changing a phase of a phase change layer.
2. Description of the Prior Art
In general, the memory devices are mainly classified as (1) random access memory (RAM) devices, which are volatile memory devices that lose information stored therein when power is shut off, and (2) read only memory (ROM) devices, which are non-volatile memory device that retain stored information even if power is shut off. Volatile RAM devices include DRAMs and SRAMs, and non-volatile ROM devices include flash memories, such as an electrically erasable and programmable ROM (EEPROM).
However, although DRAM devices are generally known in the art to be superior memory devices, they require a high charge storage capability. For this reason, the DRAM devices must increase the surface area of an electrode, and this requirement does not help high integration design of the DRAM devices.
The flash memories include two gates aligned in a stacked structure, and they require an operating voltage that is higher than the power supply voltage. For this reason, the flash memories require separate boost circuit to generate the suitable voltage needed for writing and erasing operations. This also does not help to achieve the high integration design of flash memories.
These days, studies and researches on new types of memory devices having both the characteristics of the non-volatile memory devices and the capability of obtaining high integration with relatively simple structure have been carried out. An outcome of such studies points to the phase change RAM devices.
In a phase change RAM device, the phase of a phase change layer interposed between top and bottom electrodes is changed from a crystalline state to an amorphous state by applying the current between the top and bottom electrodes. The phase change RAM device reads out information stored in a cell based on variation of resistance between the crystalline state and the amorphous state.
A phase change RAM device employs a chalcogenide layer as a phase change layer. The chalcogenide layer includes the compound consisting of Ge, Sb and Te, and the phase of the chalcogenide layer is changed between the amorphous state and the crystalline state caused by joule heat of the current applied to the chalcogenide layer. Based on the fact that specific resistance of the phase change layer having the amorphous state is higher than that of the phase change layer having the crystalline state, the current flowing through the phase change layer is detected in the write and read modes, thereby determining if information stored in the phase change memory cell is logic “1” or logic “0”.
FIG. 1 is a cross-sectional view showing a conventional phase change RAM device.
As shown in FIG. 1, gates 4 are formed on an active area of a semiconductor substrate 1 defined by an isolation layer (not shown). In addition, a junction area (not shown) is formed at both sides of gates 4 on the upper surface of the semiconductor substrate 1.
An interlayer insulating film 5 is formed on the entire surface of the semiconductor substrate 1 such that the gates 4 are covered with the interlayer insulating film 5. A first tungsten plug 6a is formed on a first predetermined area of the interlayer insulating film 5 where the phase change cell is formed later and a second tungsten plug 6b is formed on a second predetermined area of the interlayer insulating film 5 to which the ground voltage (Vss) is applied later.
A first oxide layer 7 is formed on the interlayer insulating film 5 including the first and second tungsten plugs 6a and 6b. Although not illustrated in detail, a dot type metal pad 8 is formed on the first predetermined area of the interlayer insulating film 5, in which the phase change cell is formed later, such that the dot type metal pad 8 can make contact with the first tungsten plug 6a and a bar type ground line (i.e., a Vss line) 9 is formed on the second predetermined area of interlayer insulating film 5, to which the Vss voltage is applied, in such a manner that the bar type ground line 9 can make contact with the second tungsten plug 6b. 
A second oxide layer 10 is formed on the first oxide layer 7 including the dot type metal pad 8 and the bar type ground line 9. In addition, a bottom electrode 11 in the form of a plug is formed in a predetermined area of the second oxide layer 10, on which the phase change cell is to be formed, in such a manner that the bottom electrode 11 can make contact with the dot type metal pad 8.
In addition, a phase change layer 12 and a top electrode 13 are stacked on the second oxide layer 10 in the form of a pattern in such a manner that the top electrode 13 makes contact with the bottom electrode 11. Thus, the phase change cell consisting of the plug type bottom electrode 11, the phase change layer 12 stacked on the bottom electrode 11, and the top electrode 13 stacked on the phase change layer 12 is obtained.
A third oxide layer 14 is formed on the second oxide layer 10 such that the phase change cell is covered with the third oxide layer 14, and a metal wiring 15 is formed on the third oxide layer 14 such that the metal wiring 15 makes contact with the top electrode 13.
In order to change the phase of the phase change layer 12 in a prior art phase change RAM device having, for example, the above structure, a relatively high current flow above 1 mA is required. Thus, it is necessary to lower the current required for changing the phase of the phase change layer 12 by reducing the contact area between the phase change layer 12 and the electrode. For this reason, the plug type bottom electrode 11 is conventionally fabricated in a size less than 100 nm through an electron-beam (E-beam) process.
However, because the E-beam process is unstable, the bottom electrode 11 fabricated through the E-beam process cannot be uniformly formed throughout the predetermined area of the semiconductor substrate. When the contact area between the bottom electrode 11 and the phase change layer 12 cannot be evenly formed over the entire predetermined area of the semiconductor substrate, an increased current is required to the phase change layer such as during a write mode.
Thus, there are limitations in the conventional phase change RAM devices to reducing the contact area between the phase change layer and the bottom electrode, making these conventional devices difficult to lower the current required for changing the phase of the phase change layer.